\doxysection{WWDG\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_w_w_d_g___type_def}{}\label{struct_w_w_d_g___type_def}\index{WWDG\_TypeDef@{WWDG\_TypeDef}}


Window WATCHDOG.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_w_w_d_g___type_def_a4caf530d45f7428c9700d9c0057135f8}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_w_w_d_g___type_def_adcd6a7e5d75022e46ce60291f4b8544c}{CFR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_w_w_d_g___type_def_a15655cda4854cc794db1f27b3c0bba38}{SR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Window WATCHDOG. 

\label{doc-variable-members}
\Hypertarget{struct_w_w_d_g___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_w_w_d_g___type_def_adcd6a7e5d75022e46ce60291f4b8544c}\index{WWDG\_TypeDef@{WWDG\_TypeDef}!CFR@{CFR}}
\index{CFR@{CFR}!WWDG\_TypeDef@{WWDG\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CFR}{CFR}}
{\footnotesize\ttfamily \label{struct_w_w_d_g___type_def_adcd6a7e5d75022e46ce60291f4b8544c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t WWDG\+\_\+\+Type\+Def\+::\+CFR}

WWDG Configuration register, Address offset\+: 0x04 \Hypertarget{struct_w_w_d_g___type_def_a4caf530d45f7428c9700d9c0057135f8}\index{WWDG\_TypeDef@{WWDG\_TypeDef}!CR@{CR}}
\index{CR@{CR}!WWDG\_TypeDef@{WWDG\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_w_w_d_g___type_def_a4caf530d45f7428c9700d9c0057135f8} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t WWDG\+\_\+\+Type\+Def\+::\+CR}

WWDG Control register, Address offset\+: 0x00 \Hypertarget{struct_w_w_d_g___type_def_a15655cda4854cc794db1f27b3c0bba38}\index{WWDG\_TypeDef@{WWDG\_TypeDef}!SR@{SR}}
\index{SR@{SR}!WWDG\_TypeDef@{WWDG\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SR}{SR}}
{\footnotesize\ttfamily \label{struct_w_w_d_g___type_def_a15655cda4854cc794db1f27b3c0bba38} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t WWDG\+\_\+\+Type\+Def\+::\+SR}

WWDG Status register, Address offset\+: 0x08 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
